<?xml version="1.0" encoding="UTF-8"?>
<Project>
    <Project_Created_Time>2022-11-07 00:53:28</Project_Created_Time>
    <TD_Version>4.6.30127</TD_Version>
    <UCode>11010110</UCode>
    <Name>RiscvSOC</Name>
    <HardWare>
        <Family>EG4</Family>
        <Device>EG4S20NG88</Device>
    </HardWare>
    <Source_Files>
        <Verilog>
            <File>../../RTL/soc/yadan_riscv_sopc.v</File>
            <File>../../RTL/core/yadan_riscv.v</File>
            <File>../../RTL/core/cpu_ahb_if.v</File>
            <File>../../RTL/core/cpu_ahb_mem.v</File>
            <File>../../RTL/core/csr_reg.v</File>
            <File>../../RTL/core/ctrl.v</File>
            <File>../../RTL/core/ex.v</File>
            <File>../../RTL/core/ex_mem.v</File>
            <File>../../RTL/core/id.v</File>
            <File>../../RTL/core/id_ex.v</File>
            <File>../../RTL/core/if_id.v</File>
            <File>../../RTL/core/mem.v</File>
            <File>../../RTL/core/mem_wb.v</File>
            <File>../../RTL/core/pc_reg.v</File>
            <File>../../RTL/core/regsfile.v</File>
            <File>../../RTL/core/yadan_defs.v</File>
            <File>../../RTL/core/muldiv/absolute_value.v</File>
            <File>../../RTL/core/muldiv/long_slow_div_denom_reg.v</File>
            <File>../../RTL/core/muldiv/mul_div_32.v</File>
            <File>../../RTL/periphery/amba_ahb_m2s5.v</File>
            <File>../../RTL/ram/AHB2MEM_RAM.v</File>
            <File>../../RTL/ram/AHB2MEM_ROM.v</File>
            <File>../../RTL/al_ip/boot_rom.v</File>
            <File>../../RTL/al_ip/dataram.v</File>
            <File>../../RTL/al_ip/datarom.v</File>
            <File>../../RTL/periphery/ahb_apb_9.v</File>
            <File>../../RTL/periphery/apb_gpio.v</File>
            <File>../../RTL/periphery/timer/apb_timer.v</File>
            <File>../../RTL/periphery/timer/timer.v</File>
            <File>../../RTL/periphery/spi_master/apb_spi_master.v</File>
            <File>../../RTL/periphery/spi_master/spi_master_apb_if.v</File>
            <File>../../RTL/periphery/spi_master/spi_master_clkgen.v</File>
            <File>../../RTL/periphery/spi_master/spi_master_controller.v</File>
            <File>../../RTL/periphery/spi_master/spi_master_fifo.v</File>
            <File>../../RTL/periphery/spi_master/spi_master_rx.v</File>
            <File>../../RTL/periphery/spi_master/spi_master_tx.v</File>
        </Verilog>
        <VHDL>
            <File>../../RTL/periphery/uart_apb/apb_uart.vhd</File>
            <File>../../RTL/periphery/uart_apb/slib_clock_div.vhd</File>
            <File>../../RTL/periphery/uart_apb/slib_counter.vhd</File>
            <File>../../RTL/periphery/uart_apb/slib_edge_detect.vhd</File>
            <File>../../RTL/periphery/uart_apb/slib_fifo.vhd</File>
            <File>../../RTL/periphery/uart_apb/slib_input_filter.vhd</File>
            <File>../../RTL/periphery/uart_apb/slib_input_sync.vhd</File>
            <File>../../RTL/periphery/uart_apb/slib_mv_filter.vhd</File>
            <File>../../RTL/periphery/uart_apb/uart_baudgen.vhd</File>
            <File>../../RTL/periphery/uart_apb/uart_interrupt.vhd</File>
            <File>../../RTL/periphery/uart_apb/uart_receiver.vhd</File>
            <File>../../RTL/periphery/uart_apb/uart_transmitter.vhd</File>
        </VHDL>
        <ADC_FILE>../Yadan.adc</ADC_FILE>
        <SDC_FILE>../Yadan.sdc</SDC_FILE>
        <CWC_FILE/>
    </Source_Files>
    <TOP_MODULE>
        <LABEL/>
        <MODULE>yadan_riscv_sopc</MODULE>
        <CREATEINDEX>auto</CREATEINDEX>
    </TOP_MODULE>
    <Project_Settings>
        <Step_Last_Change>2022-11-08 23:09:24</Step_Last_Change>
        <Current_Step>60</Current_Step>
        <Step_Status>true</Step_Status>
    </Project_Settings>
</Project>
